Innovation in silicon process technology continues to improve the performance and functionality of integrated circuits (“ICs”) at decreasing production costs. These improvements proliferate the electronics and information processing industries, which exact increased demands upon the IC design industry for even faster and cheaper devices.
Over the past two decades, the IC design industry has become increasingly reliant upon a variety of computer-aided design (“CAD”) tools. One such category of CAD tools is IC simulators which operate to define and represent ICs as a list of statements in a Hardware Description Language (“HDL”), such as Verilog, VHDL, or the like.
Such HDL simulators enable IC designers to enter behavior-like descriptions of logic circuit elements, or modules, and, more broadly, to describe the behavior of ICs in a variety of forms, including logic equations, truth tables, state diagrams, and the like. These simulators operate to compile associated circuit element descriptions into IC designs for simulation, modification and subsequent implementation.
Arguably, one of the most widely used HDL simulators is Verilog, which is operable to both design and document electronic systems. Verilog (i.e., Verify Logic) originated in the mid-1980s at Automated Integrated Design Systems, Inc. (later known as Gateway Design Automation, Inc.). Verilog was designed by Philip Moorby, who later became the Chief Designer for Verilog-XL and the first “Corporate Fellow” at Cadence Design Systems, Inc. Gateway Design Automation grew rapidly with the success of Verilog-XL and was acquired by Cadence Design Systems in 1989.
Verilog was invented as a simulation language, and its use for synthesis was an afterthought.
In the late-1980s, most designers were moving away from proprietary languages, like Verilog, and towards the United States Department of Defense HDL standard, known as Very High Speed Integrated Circuit (“VHSIC”) HDL. In 1990, undebatably due to market pressure, Cadence Design Systems announced its decision to open the Verilog language to the public, thereby creating Open Verilog International (“OVI”). When OVI was formed, a number of small companies began working on Verilog-based simulators, including Chronologic Simulation, Inc., Frontline Design Automation, Inc. and others. The first of these simulators became available in 1992, though now there are many Verilog simulators available from a plethora of sources.
The Verilog simulation market grew substantially during the 1990s (e.g., estimations are that sales of Verilog-related tools accounted for more than $75,000,000 in 1994 and over $150,000,000 in 1998), making Verilog the most commercially significant HDL on the market. An IEEE work group was established in 1993 under a design automation subcommittee to produce the IEEE Verilog standard.
In 1995, Verilog became IEEE Standard 1364. The IEEE standardization process includes enhancements and refinements, and, to that end, work recently completed on the Verilog 1364-2000 standard.
In recent years, in response to continued demands from the IC design industry, simulation system design has been moving toward block-based design, in which a desired IC system is designed and simulated by integrating a plurality of existing component design blocks or modules. These pre-designed blocks/modules are commonly generated by internal design teams, licensed from other design companies, or the like, and may be supported by fundamentally different design structures and environments.
In this manner, the circuit designer accepts a system specification as input and ultimately provides a netlist-level design for physical implementation (including design place, route, and verification). If design specifications are within the capabilities of the intended or available processing technology, including clocking, power, and size specifications, the available design methodology is reasonably predictable and works well with available circuit design tools.
Available methodologies allow for, or enable, the use and re-use of pre-designed circuit blocks/modules from multiple sources in a circuit design. This affords tremendous flexibility to the circuit designer. A shortcoming however arises when timing violations occur among circuit modules during simulation and the HDL system generates notifier signals in response to timing check commands. These timing check commands inhibit and may even preclude continued testing of those circuit modules associated with the timing violation, as well as related circuit modules.
There exists a need in the art for a system that selectively disables timing-violation notifications in HDL IC models, as well as methods of operating the same. There exists a further need in the art for a system and a related method that selectively modifies behavior of notifier signals in response to such timing-violation notifications.